1. Technical Field
The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.
2. Description of Related Art
As a memory device (particularly, a flash memory) has a larger capacity, the short channel effect caused by a finer transistor increases. It becomes to make difficult to control threshold voltage, which causes remarkable degradation of the memory cell characteristic of operations such as writing, reading, etc. Accordingly, it is difficult to manufacture a large-capacity memory. As a memory cell becomes finer, the contact area between a floating gate electrode (FG) and a control gate electrode (CG) formed via an intergate insulation film decreases. Thus, the capacitance between the CG and the FG lowers, and a large CG bias is required to apply a sufficient potential to a channel, which may cause degradation of the insulating film between the CG and the FG and increase leak current. Thus, there is a large problem of how to improve a writing efficiency and lower the CG voltage during a writing operation.
To obtain a finer transistor, it is necessary to reduce the gate width and the channel length of a memory cell transistor. However, it is difficult to thin a gate insulating film, a floating gate polysilicon electrode layer, and an intergate insulating film formed between the floating and control gates which are stacked in a vertical direction because of the electric characteristic. Thus, the electric gate insulating film thickness viewed from the control gate electrode cannot be thinned. Consequently, the cutoff characteristic of the transistor is degraded, which is a problem in making the transistor finer.
A vertex channel array transistor (VCAT) formed on a bulk silicon substrate is applied to a trench capacitor DRAM for the first time (see M. Kito et al., “Vertex Channel Array Transistor (VCAT) Featuring sub-60 nm High Performance and manufacturable Trench Capacitor DRAM,” 2005 Symposium on VLSI Technology Digest of Technical Papers, 3B-1, pp. 32-33). The VCAT utilizes vertexes as a channel between a top surface and (111) facet of a selective epitaxial silicon grown on active areas. The VCAT can be fabricated with a much simpler process than FIN array transistor and fit to the process integration of a trench capacitor DRAM cell. According to this VCAT, almost 2 times higher on-current, smaller sub-threshold swing and less body effect than a planar array transistor are demonstrated.